Dimming LEDs (part 3/3) – The overlooked boundaries

In the last PWM discussion, we devised how is composed the average current, specially when the PWM frequency is faster than it should be, making the period duration comparable with the rise and fall slopes duration of the current. The results were packed up in 2 equations to summarize what is the best choice for the PWM period. This was expressed with the maximum frequency (eq. 33 from the last article) and the minimum (eq. 34), namely:

$T_{min} = t_{on-min} + t_{off-min}$ (1)

$T >> T_{min}$ (2)

From which, developing the time duration of the minimum on-time and off-time, given the system architecture, is possible to find a practical value of the period.

How much slow the PWM signal can be?

In many cases, the PWM frequency has also a lower limit which depends on the application. If human eye is involved, there is the flicker fusion threshold involved. This has been noted being not lower than 50 Hz; even though we are very edgy here. But during saccades (saccadic eye movement, or moving our sight from one point to another), frequencies up to 2 or 3 kHz can be easily detected.
In fact, by moving the eye durin a saccadic movement, which happens relatively fast, the light will continuously hit a different part of the retina, behaving exactly like an oscilloscope, excuse me the analogy. Or, like a camera which is moved during a shot. A picture of what you would see during a saccadic while staring initially to a LED light with some random blinking, is shown here in Figure 1.

Figure 1 – Frame shot on a moving, blinking LED. (Aperture time 1/5, similar to our rod photoreceptor cells‘ time constant)

A scope acquisition of the same signal is shown here:

Figure 2 – Probing the electrical signal of the LED light up in Figure 1.

Now is more clear what I mean when the eye is acting as a scope. I presume this delay in our eyes is to give time to the brain to get the image better at the subconsciuous level. But I leave this to the experts.

As a result, also the lower limit depends on the application. If no blink artifact (like in Figure 1) shall be visible at any condition, more than 3kHz is a good starting point. Otherwise, 60 or maybe 100 Hz is good enough, making the design of the PWM less troublemaker under the EMC point of view.

Architecting the digital part: how many bits?

After all the considerations so far, it is possible to finally drive the LED! But sometimes (i.e. always in the real world) is required a certain minimum resolution. This translated in the requirements of how many bits are required when generating the PWM signal.

With a generic n-bit PWM, the available steps are $2^{n}$ , ranging from $0$ to $(2^{n} - 1)$ , meaning that in general the resolution of the duty cycle $p$ is:

$p = \frac{1}{2^{n_{bits}}} \cdot T_{pwm}$ (3)

First, since a duty cycle of 100% means an always-on signal, thus is only DC in the spectrum, the minimum value below 100% shall comply with the $t_{off-min}$ explained in the Part 2/3. Secondly, the duty cycle of 0% means an always-off signal and the minimum value above this percentage shall comply again with the $t_{on-min}$ . Now, in a digital system, the minimum value is literally a “bit” less for the 100% case, and a “bit” more for the 0% case. To be able to exploit the full range, this “bit” shall have a duration higher than the longer time chosen among $t_{off-min}$ and $t_{on-min}$ .

Just to recap, the $t_{off-min}$ is the minimum time required to let the driver turn off, to settle, so depends mainly on the slope $S_f$ and its duration:

$t_{off-min} = \frac{I_{max}}{S_f}$ (4)

while the $t_{on-min}$ shall overcome the delay of the driver $t_d$ and the slope duration of the rising current:

$t_{on-min} = t_d + \frac{I_{max}}{S_r}$ (5)

Since the maximum duty cycle is $\frac{(2^{n} - 1)}{(2^{n} - 1)}$ (becase the minimum is 0 and is included in the scale), subtracting one bit more lead to $\frac{(2^{n} - 2)}{(2^{n} - 1)}$ which is the maximum duty cycle achievable lower than the 100%. Conversely, from a minimum duty cycle of 0, adding one will lead to a minimum time in which the PWM signal is on in one cycle, $\frac{1}{(2^{n} - 1)}$ .

To comply with the first requirement to properly deal with the analog capabilities of the driver, the minium on-time shall be as long as at least the time duration of a single bit in the PWM word:

$\frac{1}{(2^{n} - 1)}\cdot T \geq t_{on-min}$ (6)

This automatically bind to the Dimming Ratio requirement, as briefly mentioned the Part 1/3. It was found that the Dimming Ratio is:

${DR} = \frac{T_{pwm}}{t_{on-min}} : 1$ (7)

which translates from (6) into:

${DR} = \frac{T_{pwm}}{\frac{1}{(2^{n} - 1)}\cdot T_{pwm}} : 1 = (2^{n}-1) : 1$ (8)

The (eq. 8) shall be compared with the analog counter part. This means that to find the minimum required number of bits, the (eq. 6) shall be reversed for $n$ bits and taking the next round value for it, which are the maximum required/suggested number of bits:

$n \geq \left\lceil{{log}_2 \left (\frac{T_{pwm}}{t_{on-min}}+1\right )} \right \rceil$ (7)

Yes, the sign $\leq$ is intentional, as this is the minimum number of bits in order to use all the digital control dynamics, while staying within the boundaries of the (eq. 6). More bits are of course a better choice, but to keep proper dimming at the firsts and lasts duty-cycle word values, the step increase/decrease shall fall within a magnitude equal to the bits from (eq. 7). Therefore any resolution can be used, but what matters is that the steps shall be bigger than the duration imposed by the analog circuitry from the fully off state to the first bit of PWM, and viceversa from the fully on state.

Few more words on the suggetsed maximum number of bits

If proper precision is required to all the PWM steps, the (eq. 7) apply only at the first and the last PWM step. Which mean that once the current reached the right value, an “infinitesimal” step increase can be applied (i.e. with infinine number of bit of PWM word, giving no quantization error). So while in the middle of the dynamics, a more resolution can be deployed; but for sake of simplicity, almost everywhere is used a fixed PWM resolution.

What is important is to get to know the error introduced by the digital control: the simple way here is to take into account the equivalent DC output from the PWM, and how does it drift from an ideal infinite resolution PWM system.

First, the precision here is mainly related to the analog front-end of the driver. It is known that there are ramps of finite amount of time, greater than 0, of duration from eq. 4 and 5, namely $t_{on-min}$ and $t_{off-min}$ . Those are affecting the effective required on-time quantity of a tiny amount, which can be devised from the equation found in the previous article – Part 2/3.

The Eq. 7 shows what is the number of bits to be used in the PWM controller to “hide” those analog errors (i.e. the ramps). If we call the number found in the Eq. 7 $n_{min}$ and the actual number of bits used are called $n$ , then Figure 3 shows how the right number of bits can bring a step long enough to let the ramp settle:

Figure 3 – Using a number of bits greater than required (dashed lines) and the right amount (continuous lines)

Lowering $n$ further is unnecesary, while increasing expose us to the uncertainty of the ramps (see dashed lines in Figure 3). So that does not means that those non-ideal effects are gone, but are just kept confined in time. This time is represented by $t_{on-min}$ in Eq. 5. Assuming we are respecting the minimum PWM period (from Eq. 1), referring to equations 15-18 in Part 2/3, is possible to consider the settled on-time by removing the duration of the delay and the ramp:

$t_{on-real} = t_{on} - t_{d} - \frac{I_{max}}{S_r}$ (8)
$I_{avg-real} = \frac{t_{on-real}}{T}$ (8a)

the relative error is given by the ratio of Eq. 8a with the ideal average current:

$\varepsilon_{I_{avg}} = \frac{\frac{t_{on-real}}{T}}{\frac{t_{on}}{T}} = \frac{t_{on-real}}{t_{on}}$ (9)

Regarding the resolution, if the ramps are necessary to reach their steady state and the delay of the real analog driver is considered, then the number of bits $n$ from Eq. 7 are used, the resolution will be, as mentioned at the beginning $p = \frac{1}{2^n - 1}$ equivalent to a duration of $p_t = \frac{T}{2^n - 1}$ .

ALEA

e × engineer

Dimming LEDs (part 3/3) – The overlooked boundaries

How much slow the PWM signal can be?

Architecting the digital part: how many bits?

Few more words on the suggetsed maximum number of bits

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How much slow the PWM signal can be?

Architecting the digital part: how many bits?

Few more words on the suggetsed maximum number of bits

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